K60P100M100SF2RM Datasheet, PDF (310/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
Transition #
11
Table 13-2. Power mode transition triggers (continued)
From
VLPR
To
VLLS(3,2,1)
Trigger Conditions
LPLLSM = (see PMCTRL register description for VLLS
configuration),
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, controlled in System Control Register in ARM core
13.1.2.2 Run Modes
The device contains two different run modes:
• Run
• Very low power run (VLPR)
13.1.2.2.1 Run Mode
This is the normal operating mode for the device.
This mode is selected after any reset. When the ARM processor exits reset, it sets up the
stack, program counter (PC), and link register (LR):
• The processor reads the start SP (SP_main) from vector-table offset 0x000
• The processor reads the start PC from vector-table offset 0x004
• LR is set to 0xFFFF_FFFF.
To reduce power in this mode, disable unused modules by clearing the peripherals
corresponding clock gating control bit in the SIM's registers.
13.1.2.2.2 Very Low Power Run (VLPR) Mode
In VLPR, the on-chip voltage regulator is put into a stop mode regulation state. In this
state, the regulator is designed to supply enough current to the MCU over a reduced
frequency. To further reduce power in this mode, disable the clocks to unused modules in
the peripherals' corresponding clock gating control bits in the SIM's registers.
Before entering this mode, the following conditions must be met:
• One of two clock sources selected:
• Either BLPE is the selected clock mode for the MCG or
• BLPI with the 2MHz IRC.
• The system, bus, and core frequency is 2 MHz or less.
• Flash frequency is 1 MHz or less.
• Mode protection must be set to allow VLP modes (AVLP = 1).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
310
Freescale Semiconductor, Inc.