K60P100M100SF2RM Datasheet, PDF (365/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 17 Crossbar Switch (AXBS)
AXBS memory map (continued)
Absolute
address
(hex)
Register name
4000_4600 Priority Registers Slave (AXBS_PRS6)
4000_4610 Control Register (AXBS_CRS6)
4000_4700 Priority Registers Slave (AXBS_PRS7)
4000_4710 Control Register (AXBS_CRS7)
4000_4800
Master General Purpose Control Register
(AXBS_MGPCR0)
4000_4900
Master General Purpose Control Register
(AXBS_MGPCR1)
4000_4A00
Master General Purpose Control Register
(AXBS_MGPCR2)
4000_4B00
Master General Purpose Control Register
(AXBS_MGPCR3)
4000_4C00
Master General Purpose Control Register
(AXBS_MGPCR4)
4000_4D00
Master General Purpose Control Register
(AXBS_MGPCR5)
4000_4E00
Master General Purpose Control Register
(AXBS_MGPCR6)
4000_4F00
Master General Purpose Control Register
(AXBS_MGPCR7)
Width
(in bits)
Access
Reset value
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17.2.1 Priority Registers Slave (AXBS_PRSn)
The priority registers (PRSn) set the priority of each master port on a per slave port basis
and reside in each slave port. The priority register can be accessed only with 32-bit
accesses. After the CRSn[RO] bit is set, the PRSn register can only be read; attempts to
write to it have no effect on PRSn and result in a bus-error response to the master
initiating the write.
No two available master ports may be programmed with the same priority level. Attempts
to program two or more masters with the same priority level result in a bus-error response
and the PRSn is not updated.
NOTE
The possible values for the PRSn fields depend on the number
of masters available on the device. See the device's Chip
Configuration details for the number of masters supported.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
365