K60P100M100SF2RM Datasheet, PDF (121/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
ADCx_SE4a
ADCx_SE5a
ADCx_SE6a
ADCx_SE7a
ADCx_SE4b
ADCx_SE5b
ADCx_SE6b
ADCx_SE7b
AD4 [00100]
AD5 [00101]
AD6 [00110]
AD7 [00111]
ADC
Figure 3-37. ADCx_SEn channels a and b selection
3.7.1.6 ADC Hardware Interleaved Channels
The AD8 and AD9 channels on ADCx are interleaved in hardware using the following
configuration.
ADC0_SE8/ADC1_SE8
ADC0
AD8
ADC0_SE9/ADC1_SE9
AD9
ADC1
AD8
AD9
Figure 3-38. ADC hardware interleaved channels integration
3.7.1.7 ADC and PGA Reference Options
The ADC supports the following references:
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
121