K60P100M100SF2RM Datasheet, PDF (1569/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

52.2.2 SDHC block diagram
DMA request
Crossbar switch
master port
Advanced DMA
Configurable
Buffer
Controller
Peripheral bus
Clocks
R/W
Register
Bank
Internal Dual-Port
128x32-bit Buffer
RAM
Chapter 52 Secured digital host controller (SDHC)
CMD Channel
State Machine
Logic
Control
CRC
Logic
Data Channel Control
State Machine _CRC
CMD/
Data
Channel
Tx/Rx
Handler
CMD
DAT7
DAT6
DAT5
DAT4
DAT3
Interrupt
Status Register
Interrupt
Controller
SD Bus
Monitor & Gating
Clock Controller and Reset manager
DAT2
DAT1
DAT0
SD_CLK
SD_CD#
SD_WP
SD_LCTL
SD_VS
Figure 52-2. Enhanced secure digital host controller block diagram
52.2.3 Features
The features of the SDHC module include the following:
• Conforms to the SD Host Controller Standard Specification version 2.0 including test
event register support
• Compatible with the MMC System Specification version 4.2/4.3
• Compatible with the SD Memory Card Specification version 2.0 and supports the
high capacity SD memory card
• Compatible with the SDIO Card Specification version 2.0
• Compatible with the CE-ATA Card Specification version 1.0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1569