K60P100M100SF2RM Datasheet, PDF (195/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

6.2.2.1 External pin reset (PIN)
Chapter 6 Reset and Boot
On this device, RESET is a dedicated pin. This pin is open drain and has an internal
pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the
SRSL[PIN] bit is set.
6.2.2.1.1 Reset pin filter
The RESET pin supports digital filtering in all modes of operation. For LLS and VLLSx
modes, the LLWU provides an optional fixed digital filter running off the 1 kHz LPO
clock. See the LLWU chapter for operation of this filter. During non-low leakage
operation, there are two clock options for the RESET pin filter – the 1kHz LPO clock and
the bus clock.
This RESET pin filter implemented in SIM logic includes a separate filter for each clock
source. In Stop and VLPS operation this logic either switches to bypass operation or has
continued filtering operation depending on the filtering mode selected.
There are several modes defined – See the SOPT6 register description in module for
more details. SOPT6[RSTFLTEN[2:0]] and SOPT6[RSTFLTSEL[4:0]] fields control the
desired functionality. Both filters are reset on POR, LVD, and wakeup from VLLS. The
reset value for each filter defaults to off (non-detect).
The LPO filter is simple with a fixed filter value count of 3. There is also a synchronizer
on the input signal that results in an associated latency (2 cycles). As such, it takes 5
cycles to complete a transition from low-to-high or high-to-low. The LPO Filter
initializes to off (logic 1) when the LPO filter is not enabled.
The Bus Filter initializes to off (logic 1) when the Bus Filter not enabled. When the Bus
Filter is enabled, the number of counts is controlled by SOPT6[RSTFLTSEL[4:0]].
6.2.2.2 Low-voltage detect (LVD) reset
This device includes a system to protect against low voltage conditions to protect
memory contents and control MCU system states during supply voltage variations. The
system is comprised of a power-on reset (POR) circuit and a low-voltage detect (LVD)
circuit with a user-selectable trip voltage, either high (V_LVDH) or low (V_LVDL). The trip
voltage is selected by the LVDSC1[LVDV] bits. The LVD system is always enabled in
normal run, wait, and stop modes. The LVD system is disabled in VLPx, LLSx, and
VLLSx modes. Refer to Power Management Controller (PMC) chapter for more details.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
195