K60P100M100SF2RM Datasheet, PDF (1221/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 44 10/100-Mbps Ethernet MAC (ENET)
Table 44-87. Enhanced Transmit Buffer Descriptor Field Definitions (continued)
Word
Offset + 10
Offset + 12
Offset + 14
Offset + 16
Offset + 18–Offset +
1E
Field
14–0
15–0
15–0
1588 timestamp
15–0
Description
Reserved, must be cleared.
Reserved, must be cleared.
This value is written by the uDMA . It is only valid if the L bit is set.
Reserved, must be cleared.
44.4.15 Client FIFO Application Interface
The FIFO interface is completely asynchronous from the Ethernet line, and the transmit
and receive interface can operate at a different clock rate.
All transfers to/from the user application are handled independent of the core operation,
and the core provides a simple interface to user applications based on a two-signal
handshake.
44.4.15.1 Data Structure Description
The data structure defined in the following tables for the FIFO interface must be
respected to ensure proper data transmission on the Ethernet line. Byte 0 is sent to and
received from the line first.
Table 44-88. FIFO Interface Data Structure
63
56 55
48 47
40 39
32 31
24 23
16 15
87
0
Word 0 Byte 7
Byte 6
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Byte 0
Word 1 Byte 15 Byte 14 Byte 13 Byte 12 Byte 11 Byte 10 Byte 9
Byte 8
... ...
The size of a frame on the FIFO interface may not be a modulo of 64-bit.
The user application may not care about the Ethernet frame formats in full detail. It needs
to provide and receive an Ethernet frame with the following structure:
• Ethernet MAC destination address
• Ethernet MAC source address
• Optional 802.1q VLAN Tag (VLAN type and info field)
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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