K60P100M100SF2RM Datasheet, PDF (1455/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 50 Inter-Integrated Circuit (I2C)
50.3.9
I2C SMBus Control and Status register (I2Cx_SMB)
NOTE
When the SCL and SDA signals are held high for a length of
time greater than the high timeout period, the SHTF1 flag sets.
Before reaching this threshold, while the system is detecting
how long these signals are being held high, a master assumes
that the bus is free. However, the SHTF1 bit rises in the bus
transmission process with the idle bus state.
NOTE
When the TCKSEL bit is set, there is no meaning to monitor
the SHTF1 bit because the bus speed is too high to match the
protocol of SMBus.
Addresses: I2C0_SMB is 4006_6000h base + 8h offset = 4006_6008h
I2C1_SMB is 4006_7000h base + 8h offset = 4006_7008h
Bit
Read
Write
Reset
7
FACK
0
6
5
ALERTEN SIICAEN
0
0
4
TCKSEL
0
3
SLTF
w1c
0
2
SHTF1
0
1
SHTF2
w1c
0
0
SHTF2IE
0
I2Cx_SMB field descriptions
Field
7
FACK
Fast NACK/ACK enable
Description
For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the
result of receiving data byte.
6
ALERTEN
0 An ACK or NACK is sent on the following receiving data byte
1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a
data byte generates a NACK.
SMBus alert response address enable
Enables or disables SMBus alert response address matching.
NOTE: After the host responds to a device that used the alert response address, you must use software
to put the device's address on the bus. The alert protocol is described in the SMBus
specification.
5
SIICAEN
0 SMBus alert response address matching is disabled
1 SMBus alert response address matching is enabled
Second I2C address enable
Enables or disables SMBus device default address.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1455