K60P100M100SF2RM Datasheet, PDF (1664/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/application of SDHC
3. Software then need to configure BLKATTR register to set block size/no. In DMA
mode, it is better to set block number to the max value(16'hffff).
4. Software need to configure PROCTL[DTW].
5. Software enable ADMA2 by configuring PROCTL[DMAS].
6. Software need to set at least three pairs ADMA2 descriptor in boot memory (ie, in
IRAM, at least 6 words). The first pair descriptor define the start address (ie, IRAM)
and data length(ie,512byte*VALUE1) of first part boot code. Software also need to
set the second pair descriptor, the second start address (any value that is writable),
data length is suggest to set 1~2word (record as VAULE2). Note: the second couple
desc also transfer useful data even at lease 1 word. Because our ADMA2 can't
support 0 data_length data transfer descriptor.
7. Software need to configure CMDARG register to set argument to 0xFFFFFFFA in
alternative fast boot, and don't need set in normal fast boot.
8. Software need to configure XFERTYP register to start the boot process .
XFERTYP[CMDINX], XFERTYP[CMDTYP], XFERTYP[RSPTYP],
XFERTYP[CICEN], XFERTYP[CCCEN], XFERTYP[AC12EN],
XFERTYP[BCEN] and XFERTYP[DMAEN] are kept default value.
XFERTYP[DPSEL] bit is set to 1, XFERTYP[DTDSEL] is set to 1,
XFERTYP[MSBSEL] is set to 1. XFERTYP[DMAEN] is configured as 1 in DMA
mode. And if XFERTYP[BCEN] is configured as 1, better to configure blk no in
BLKATTR register to the max value.
9. When the step 8 is configured, boot process will begin, the first VAULE1 block
number data has transfer. Software need to polling IRQSTAT[TC] bit to determine
first transfer is end. Also software need to polling IRQSTAT[BGE] bit to determine
if first transfer stop at block gap.
10. When IRQSTAT[TC] and IRQSTAT[BGE] bits are 1, . SW can analyzes the first
code of VAULE1 block, initializes the new memory device, if required, and sets the
third pair of descriptors to define the start address and length of the remaining part of
boot code (VAULE3 the remain boot code block). Remember set the last descriptor
with END.
11. Software need to configure MMCBOOT register (offset 0xc4) again. Set
MMCBOOT[BOOTEN] bit to 1; and MMCBOOT[BOOTMODE] bit to 0 (normal
fast boot), to 1(alternative boot); and MMCBOOT[BOOTACK] bit to select the ack
mode or not. In DMA mode, configure MMCBOOT[AUTOSABGEN] bit to 1 for
enable automatically stop at block gap feature. Also configure
MMCBOOT[BOOTBLKCNT] bit to set the (VAULE1+1+VAULE3), that host will
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.