K60P100M100SF2RM Datasheet, PDF (1637/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 52 Secured digital host controller (SDHC)
SDIO interrupt status latched in the SDHC and to stop driving the interrupt signal to the
system interrupt controller. The host driver must issue a CMD52 to clear the card
interrupt. After completion of the card interrupt service, the SDIO Interrupt Enable bit is
set to 1, and the SDHC starts sampling the interrupt signal again.
The following diagram illustrates the SDIO card interrupt scheme and for the sequences
of software and hardware events that take place during a card interrupt handling
procedure.
IP Bus
IRQ to CPU
Start
eSDHC Registers
SDIO IRQ Status
SDIO IRQ Enable
Command/
Response
Handling
Enable card IRQ in Host
Detect and steer card IRQ
Read IRQ Status Register
IRQ Detecting & Steering
Disable Card IRQ in Host
SD Host
SDIO Card
IRQ0
SDIO Card
IRQ Routing
IRQ1
Interrogate and service Card IRQ
Response Error?
Yes
No
Clear Card IRQ in Card
Function 0
Clear IRQ0
Function 1
Clear IRQ1
Enable card IRQ in Host
End
Figure 52-36. Card interrupt scheme and card interrupt detection and handling
procedure
52.5.7 Card insertion and removal detection
The SDHC uses either the DAT[3] pin or the CD pin to detect card insertion or removal.
When there is no card on the MMC/SD bus, the DAT[3] will be pulled to a low voltage
level by default. When any card is inserted to or removed from the socket, the SDHC
detects the logic value changes on the DAT[3] pin and generates an interrupt. When the
DAT[3] pin is not used for card detection (for example, it is implemented in GPIO), the
CD pin must be connected for card detection. Whether DAT[3] is configured for card
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1637