K60P100M100SF2RM Datasheet, PDF (1148/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
ENET_MIBC field descriptions (continued)
Field
29
MIB_CLEAR
MIB clear
If set, all statistics counters are reset to 0.
Description
28–0
Reserved
NOTE: This bit is not self-clearing. To clear the MIB counters set and then clear the bit.
This read-only field is reserved and always has the value zero.
44.3.9 Receive Control Register (ENET_RCR)
Address: ENET_RCR is 400C_0000h base + 84h offset = 400C_0084h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R GRS
NLC
W
MAX_FL
Reset 0
0
0
0
0
1
0
1
1
1
1
0
1
1
1
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
FCE
BC_
REJ
W
Reset 0
Field
31
GRS
30
NLC
29–16
MAX_FL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
ENET_RCR field descriptions
Graceful receive stopped
Description
Read-only status indicating that the MAC receive datapath is stopped.
Payload length check disable
Enables/disables a payload length check.
0 The payload length check is disabled
1 The core checks the frame's payload length with the frame length/type field. Errors are indicated in
the EIR[PLC] bit.
Maximum frame length
Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame.
Transmit frames longer than MAX_FL cause the BABT interrupt to occur. Receive frames longer than
MAX_FL cause the BABR interrupt to occur and set the LG bit in the end of frame receive buffer
descriptor. The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
supported.
Table continues on the next page...
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.