K60P100M100SF2RM Datasheet, PDF (1488/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and registers
Addresses: UART0_BDH is 4006_A000h base + 0h offset = 4006_A000h
UART1_BDH is 4006_B000h base + 0h offset = 4006_B000h
UART2_BDH is 4006_C000h base + 0h offset = 4006_C000h
UART3_BDH is 4006_D000h base + 0h offset = 4006_D000h
UART4_BDH is 400E_A000h base + 0h offset = 400E_A000h
Bit
7
6
5
4
3
2
1
0
Read
0
LBKDIE RXEDGIE
Write
SBR
Reset
0
0
0
0
0
0
0
0
UARTx_BDH field descriptions
Field
7
LBKDIE
LIN Break Detect Interrupt Enable
Description
LBKDIE enables the LIN break detect flag, LBKDIF, to generate interrupt requests based on the state of
LBKDDMAS.
6
RXEDGIE
0 LBKDIF interrupt requests disabled.
1 LBKDIF interrupt requests enabled.
RxD Input Active Edge Interrupt Enable
RXEDGIE enables the Receive input active edge, RXEDGIF, to generate interrupt requests.
5
Reserved
4–0
SBR
0 Hardware interrupts from RXEDGIF disabled (use polling).
1 RXEDGIF interrupt request enabled.
This read-only field is reserved and always has the value zero.
UART Baud Rate Bits
The baud rate for the UART is determined by these 13 bits. See Baud rate generation for details.
NOTE: The baud rate generator is disabled until the C2[TE] bit or the C2[RE] bit is set for the first time
after reset.The baud rate generator is disabled when SBR = 0.
NOTE: Writing to BDH has no effect without writing to BDL, since writing to BDH puts the data in a
temporary location until BDL is written.
1488
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.