K60P100M100SF2RM Datasheet, PDF (1612/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
Forcing a card interrupt will generate a short pulse on the DAT[1] line, and the driver
may treat this interrupt as a normal interrupt. The interrupt service routine may skip
polling the card interrupt factor as the interrupt is self cleared.
Address: SDHC_FEVT is 400B_1000h base + 50h offset = 400B_1050h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
0
0
0
0
0
0
0
0
0
W
0
0
0
DCE
CIE
CCE
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
W
0
0
Reset 0
Field
31
CINT
30–29
Reserved
28
DMAE
27–25
Reserved
24
AC12E
23
Reserved
22
DEBE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDHC_FEVT field descriptions
Force Event Card Interrupt
Description
Writing 1 to this bit generates a short low-level pulse on the internal DAT[1] line, as if a self clearing
interrupt was received from the external card. If enabled, the CINT bit will be set and the interrupt service
routine may treat this interrupt as a normal interrupt from the external card.
This field is reserved.
Force Event DMA Error
Forces the DMAE bit of Interrupt Status Register to be set.
This field is reserved.
Force Event Auto Command 12 Error
Forces the IRQSTAT[AC12E] to be set.
This field is reserved.
Force Event Data End Bit Error
Table continues on the next page...
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.