K60P100M100SF2RM Datasheet, PDF (1108/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

CMT Interrupts and DMA
MSC[EOCF] is set when:
• The modulator is not currently active and MSC[MCGEN] bit is set to begin the
initial CMT transmission
• At the end of each modulation cycle (when the counter is reloaded from
CMD1:CMD2) while MSC[MCGEN] bit is set
In the case where MSC[MCGEN] bit is cleared and then set before the end of the
modulation cycle, MSC[EOCF] bit will not be set when MSC[MCGEN] is set, but will
become set at the end of the current modulation cycle.
When MSC[MCGEN] becomes disabled, the CMT module does not set the EOC flag at
the end of the last modulation cycle.
If MSC[EOCIE] bit is high when MSC[EOCF] bit is set, the CMT module will generate
an interrupt request or a DMA transfer request.
MSC[EOCF] bit must be cleared to prevent from being generated another event (interrupt
or DMA request) after exiting the service routine. See following table.
Table 42-19. How to clear MSC[EOCF] bit
DMA[DM
A]
0
1
MSC[EOCIE]
X
X
Description
MSC[EOCF] bit is cleared by reading the CMT modulator status and control register
MSC followed by an access of CMD2 or CMD4.
MSC[EOCF] bit is cleared by the CMT DMA transfer done.
The EOC interrupt is coincident with loading the down-counter with the contents of
CMD1:CMD2 and loading the space period register with the contents of CMD3:CMD4.
The EOC interrupt provides a means for the user to reload new mark/space values into
the modulator data registers. Modulator data register updates will take effect at the end of
the current modulation cycle. Note that the down-counter and space period register are
updated at the end of every modulation cycle, irrespective of interrupt handling and the
state of the EOCF flag.
1108
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.