K60P100M100SF2RM Datasheet, PDF (137/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
Table 3-59. Reference links to related information (continued)
Topic
Power management
Signal Multiplexing
Related module
Port control
Reference
Power management
Signal Multiplexing
3.8.4.1 LPTMR prescaler/glitch filter clocking options
The prescaler and glitch filter of the LPTMR module can be clocked from one of four
sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the
chip-specific clock assignments for this bitfield.
NOTE
The chosen clock must remain enabled if the LPTMR is to
continue operating in all required low-power modes.
LPTMR0_PSR[PCS]
00
01
10
11
Prescaler/glitch filter clock
number
0
1
2
3
Chip clock
MCGIRCLK — internal reference clock
(not available in VLPS/LLS/VLLS
modes)
LPO — 1 kHz clock
ERCLK32K — secondary external
reference clock
OSCERCLK — external reference clock
See Clock Distribution for more details on these clocks.
3.8.4.2 LPTMR pulse counter input options
The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode.
The following table shows the chip-specific input assignments for this bitfield.
LPTMR_CSR[TPS]
00
01
10
11
Pulse counter input number
0
1
2
3
Chip input
CMP0 output
LPTMR_ALT1 pin
LPTMR_ALT2 pin
Reserved
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
137