K60P100M100SF2RM Datasheet, PDF (1335/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Addresses: CAN0_IFLAG2 is 4002_4000h base + 2Ch offset = 4002_402Ch
CAN1_IFLAG2 is 400A_4000h base + 2Ch offset = 400A_402Ch
Chapter 48 CAN (FlexCAN)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUFHI
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_IFLAG2 field descriptions
Field
31–0
BUFHI
Description
Buffer MB_i Interrupt
Each bit flags the corresponding FlexCAN Message Buffer interrupt.
0 The corresponding buffer has no occurrence of successfully completed transmission or reception.
1 The corresponding buffer has successfully completed transmission or reception.
48.3.13 Interrupt Flags 1 Register (CANx_IFLAG1)
This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt
flag bit per buffer. Each successful transmission or reception sets the corresponding
IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt will be generated. The
interrupt flag must be cleared by writing 1 to it. Writing 0 has no effect.
The BUF7I to BUF5I flags are also used to represent FIFO interrupts when the Rx FIFO
is enabled. When the bit MCR[RFEN] is set the function of the 8 least significant
interrupt flags BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating
conditions of the FIFO, and BUF4TO0I are reserved.
Before enabling the RFEN, the CPU must service the IFLAG bits asserted in the Rx
FIFO region; see Section "Rx FIFO". Otherwise, these IFLAG bits will mistakenly show
the related MBs now belonging to FIFO as having contents to be serviced. When the
RFEN bit is negated, the FIFO flags must be cleared. The same care must be taken when
an RFFN value is selected extending Rx FIFO filters beyond MB7. For example, when
RFFN is 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
must be cleared.
Before updating MCR[MAXMB] field, CPU must service the IFLAG1 bits whose MB
value is greater than the MCR[MAXMB] to be updated; otherwise, they will remain set
and be inconsistent with the amount of MBs available.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1335