K60P100M100SF2RM Datasheet, PDF (1435/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

49.4.7.4 Transmit FIFO Underflow Interrupt Request
Chapter 49 SPI (DSPI)
The Transmit FIFO Underflow Request indicates that an underflow condition in the TX
FIFO has occurred. The transmit underflow condition is detected only for the DSPI,
operating in slave mode and SPI configuration . The TFUF bit is set when the TX FIFO
of a DSPI is empty, and a transfer is initiated from an external SPI master. If the TFUF
bit is set while the TFUF_RE bit in the RSER is set, an interrupt request is generated.
49.4.7.5 Receive FIFO Drain Interrupt or DMA Request
The Receive FIFO Drain Request indicates that the RX FIFO is not empty. The Receive
FIFO Drain Request is generated when the number of entries in the RX FIFO is not zero,
and the RFDF_RE bit in the RSER is set. The RFDF_DIRS bit in the RSER selects
whether a DMA request or an interrupt request is generated.
49.4.7.6 Receive FIFO Overflow Interrupt Request
The Receive FIFO Overflow Request indicates that an overflow condition in the RX
FIFO has occurred. A Receive FIFO Overflow request is generated when RX FIFO and
shift register are full and a transfer is initiated. The RFOF_RE bit in the RSER must be
set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the MCR, the data from the transfer that
generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit
is set, the incoming data is shifted in to the shift register. If the ROOE bit is cleared, the
incoming data is ignored.
49.4.8 Power Saving Features
The DSPI supports following power-saving strategies:
• External Stop mode
• Module Disable mode - Clock gating of non-memory mapped logic
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1435