K60P100M100SF2RM Datasheet, PDF (1749/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

54.1.3.1
Chapter 54 General purpose input/output (GPIO)
Detailed signal description
Table 54-2. GPIO interface-detailed signal descriptions
Signal
PORTA[31:0]
PORTB[31:0]
PORTC[31:0]
PORTD[31:0]
PORTE[31:0]
I/O
Description
I/O
General purpose input/output.
State meaning
Asserted - pin is logic one.
Negated - pin is logic zero.
Timing
Assertion - when output,
occurs on rising edge of the
system clock. For input, may
occur at any time and input
may be asserted
asynchronously to the system
clock.
Negation - when output,
occurs on rising edge of the
system clock. For input, may
occur at any time and input
may be asserted
asynchronously to the system
clock.
54.2 Memory map and register definition
Any read or write access to the GPIO memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states, except
error accesses which complete with one wait state.
Absolute
address
(hex)
GPIO memory map
Register name
Width
(in bits)
Access
Reset value
400F_F000 Port Data Output Register (GPIOA_PDOR)
32
R/W 0000_0000h
400F_F004 Port Set Output Register (GPIOA_PSOR)
32
400F_F008 Port Clear Output Register (GPIOA_PCOR)
32
400F_F00C Port Toggle Output Register (GPIOA_PTOR)
32
Table continues on the next page...
W
(always
reads
zero)
0000_0000h
W
(always
reads
zero)
0000_0000h
W
(always
0000_0000h
Section/
page
54.2.1/
1752
54.2.2/
1752
54.2.3/
1753
54.2.4/
1753
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1749