K60P100M100SF2RM Datasheet, PDF (1450/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Descriptions
I2Cx_C1 field descriptions (continued)
Field
Description
0 All DMA signalling disabled.
1 _{DMA transfer is enabled and the following conditions trigger the DMA request:}
• While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK
automatic)
• While FACK = 0, the first byte received matches the A1 register or is general call address.
If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from
master to slave, then it is not required to check the SRW. With this assumption, DMA can also be
used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite
the C1 register operation. With this assumption, DMA cannot be used.
When FACK = 1, an address or a data byte is transmitted.
50.3.4 I2C Status Register (I2Cx_S)
Addresses: I2C0_S is 4006_6000h base + 3h offset = 4006_6003h
I2C1_S is 4006_7000h base + 3h offset = 4006_7003h
Bit
Read
Write
Reset
7
TCF
1
6
IAAS
0
5
BUSY
0
4
ARBL
w1c
0
3
RAM
0
2
SRW
0
1
IICIF
w1c
0
0
RXAK
0
I2Cx_S field descriptions
Field
7
TCF
Transfer complete flag
Description
This bit sets on the completion of a byte and acknowledge bit transfer. This bit is valid only during or
immediately following a transfer to or from the I2C module. The TCF bit is cleared by reading the I2C data
register in receive mode or by writing to the I2C data register in transmit mode.
6
IAAS
0 Transfer in progress
1 Transfer complete
Addressed as a slave
This bit is set by one of the following conditions:
• The calling address matches the programmed slave primary address in the A1 register or range
address in the RA register (which must be set to a nonzero value).
• GCAEN is set and a general call is received.
• SIICAEN is set and the calling address matches the second programmed slave address.
• ALERTEN is set and an SMBus alert response address is received
• RMEN is set and an address is received that is within the range between the values of the A1 and
RA registers.
This bit sets before the ACK bit. The CPU must check the SRW bit and set TX/RX accordingly. Writing the
C1 register with any value clears this bit.
Table continues on the next page...
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.