K60P100M100SF2RM Datasheet, PDF (1693/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
9
TUE1
8
TUE0
7
TFS
6
RFS
Chapter 53 Integrated interchip sound (I2S)
I2Sx_ISR field descriptions (continued)
Description
This flag is set when the RXSR is filled and ready to transfer to RX0 register or to Rx FIFO 0 (when
enabled) and these are already full. If Rx FIFO 0 is enabled, this is indicated by RFF0 flag, else this is
indicated by the RDR0 flag. The RXSR is not transferred in this case. The ROE0 flag causes an interrupt
if IER[RIE] and IER[ROE0EN] are set.
The ROE0 bit is cleared by POR and I²S reset. It is also cleared by writing `1' to this bit. Clearing the
CR[RE] bit does not affect the ROE0 bit.
0 No overrun detected
1 Receiver overrun error occurred
Transmitter Underrun Error 1.
This flag is set when the TXSR is empty (no data to be transmitted), the TDE1 flag is set, a transmit time
slot occurs and the I<sup>2</sup>S is in two-channel mode. When a transmit underrun error occurs, the previous data
is retransmitted. In Network mode, each time slot requires data transmission (unless masked through
TMSK register), when the transmitter is enabled (CR[TE] is set).
The TUE1 flag causes an interrupt if IER[TIE] and IER[TUE1EN] are set.
The TUE1 bit is cleared by POR and I<sup>2</sup>S reset. It is also cleared by writing `1' to this bit.
0 No underrun detected
1 Transmitter underrun error occurred
Transmitter Underrun Error 1.
This flag is set when the TXSR is empty (no data to be transmitted), the TDE0 flag is set and a transmit
time slot occurs. When a transmit underrun error occurs, the previous data is retransmitted. In Network
mode, each time slot requires data transmission (unless masked through TMSK register), when the
transmitter is enabled (CR[TE] is set). The TUE0 flag causes an interrupt if IER[TIE] and IER[TUE0EN]
are set.
The TUE0 bit is cleared by POR and I²S reset. It is also cleared by writing `1' to this bit.
0 No underrun detected
1 Transmitter underrun error occurred
Transmit Frame Sync.
This flag indicates the occurrence of transmit frame sync. Data written to the TX registers during the time
slot when the TFS flag is set, is sent during the second time slot (in network mode) or in the next first time
slot (in normal mode). In network mode, the TFS bit is set during transmission of the first time slot of the
frame and is then cleared when starting transmission of the next time slot. In normal mode, this bit is high
for the first time slot. This flag causes an interrupt if IER[TIE] and IER[TFSEN] are set. The TFS bit is
cleared by POR and I²S reset.
0 No occurrence of transmit frame sync.
1 Transmit frame sync occurred during transmission of last word written to TX registers.
Receive Frame Sync.
This flag indicates the occurrence of receive frame sync. In network mode, the RFS bit is set when the
first slot of the frame is being received. It is cleared when the next slot begins to be received. In normal
mode, this bit is always high. This flag causes an interrupt if IER[RIE] and IER[RFSEN] are set. The RFS
bit is cleared by POR and I²S reset.
0 No occurrence of receive frame sync.
1 Receive frame sync occurred during reception of next word in RX registers.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1693