K60P100M100SF2RM Datasheet, PDF (1317/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
28
HALT
27
NOTRDY
26
WAKMSK
25
SOFTRST
24
FRZACK
CANx_MCR field descriptions (continued)
Chapter 48 CAN (FlexCAN)
Description
This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is set, MBs 0 to 5 cannot be
used for normal reception and transmission because the corresponding memory region (0x80-0xDC) is
used by the FIFO engine as well as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which
are used as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the minimum number
of peripheral clocks per CAN bit as described in the table "Minimum Ratio Between Peripheral Clock
Frequency and CAN Bit Rate" (in section "Arbitration and Matching Timing"). This bit can only be written
in Freeze mode as it is blocked by hardware in other modes.
0 Rx FIFO not enabled
1 Rx FIFO enabled
Halt FlexCAN
Assertion of this bit puts the FlexCAN module into Freeze Mode. The CPU should clear it after initializing
the Message Buffers and Control Register. No reception or transmission is performed by FlexCAN before
this bit is cleared. Freeze Mode cannot be entered while FlexCAN is in a low power mode.
0 No Freeze Mode request.
1 Enters Freeze Mode if the FRZ bit is asserted.
FlexCAN Not Ready
This read-only bit indicates that FlexCAN is either in Disable Mode, Doze Mode, Stop Mode or Freeze
Mode. It is negated once FlexCAN has exited these modes.
0 FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode.
1 FlexCAN module is either in Disable Mode, Doze Mode, Stop Mode or Freeze Mode.
Wake Up Interrupt Mask
This bit enables the Wake Up Interrupt generation.
0 Wake Up Interrupt is disabled.
1 Wake Up Interrupt is enabled.
Soft Reset
When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped
registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR, ESR1, ESR2,
IMASK1, IMASK2, IFLAG1, IFLAG2 and CRCR. Configuration registers that control the interface to the
CAN bus are not affected by soft reset. The following registers are unaffected: CTRL1, CTRL2, RXIMR0–
RXIMR63, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all Message Buffers.
The SOFTRST bit can be asserted directly by the CPU when it writes to the MCR Register, but it is also
asserted when global soft reset is requested at MCU level. Since soft reset is synchronous and has to
follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate
its effect. The SOFTRST bit remains asserted while reset is pending, and is automatically negated when
reset completes. Therefore, software can poll this bit to know when the soft reset has completed.
Soft reset cannot be applied while clocks are shut down in a low power mode. The module should be first
removed from low power mode, and then soft reset can be applied.
0 No reset request
1 Resets the registers affected by soft reset.
Freeze Mode Acknowledge
This read-only bit indicates that FlexCAN is in Freeze Mode and its prescaler is stopped. The Freeze
Mode request cannot be granted until current transmission or reception processes have finished.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1317