K60P100M100SF2RM Datasheet, PDF (608/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register descriptions
27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)
The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered
0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes
the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 3.
Addresses: FMC_TAGVDW3S0 is 4001_F000h base + 160h offset = 4001_F160h
FMC_TAGVDW3S1 is 4001_F000h base + 164h offset = 4001_F164h
FMC_TAGVDW3S2 is 4001_F000h base + 168h offset = 4001_F168h
FMC_TAGVDW3S3 is 4001_F000h base + 16Ch offset = 4001_F16Ch
FMC_TAGVDW3S4 is 4001_F000h base + 170h offset = 4001_F170h
FMC_TAGVDW3S5 is 4001_F000h base + 174h offset = 4001_F174h
FMC_TAGVDW3S6 is 4001_F000h base + 178h offset = 4001_F178h
FMC_TAGVDW3S7 is 4001_F000h base + 17Ch offset = 4001_F17Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
0
tag[18:6]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_TAGVDW3Sn field descriptions
Field
31–19
Reserved
18–6
tag[18:6]
5–1
Reserved
0
valid
Description
This read-only field is reserved and always has the value zero.
13-bit tag for cache entry
This read-only field is reserved and always has the value zero.
1-bit valid for cache entry
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
608
Freescale Semiconductor, Inc.