K60P100M100SF2RM Datasheet, PDF (812/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Register Definition
ADCx_CFG2 field descriptions (continued)
Field
Description
ADHSC configures the ADC for very high speed operation. The conversion sequence is altered (2 ADCK
cycles added to the conversion time) to allow higher speed conversion clocks.
1–0
ADLSTS
0 Normal conversion sequence selected.
1 High speed conversion sequence selected (2 additional ADCK cycles to total conversion time).
Long sample time select
ADLSTS selects between the extended sample times when long sample time is selected (ADLSMP=1).
This allows higher impedance inputs to be accurately sampled or to maximize conversion speed for lower
impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total).
01 12 extra ADCK cycles; 16 ADCK cycles total sample time.
10 6 extra ADCK cycles; 10 ADCK cycles total sample time.
11 2 extra ADCK cycles; 6 ADCK cycles total sample time.
34.3.4 ADC data result register (ADCx_Rn)
The data result registers (Rn) contain the result of an ADC conversion of the channel
selected by the corresponding status and channel control register (SC1A:SC1n). For
every status and channel control register, there is a corresponding data result register.
Unused bits in the Rn register are cleared in unsigned right justified modes and carry the
sign bit (MSB) in sign extended 2's complement modes. For example, when configured
for 10-bit single-ended mode, D[15:10] are cleared. When configured for 11-bit
differential mode, D[15:10] carry the sign bit (bit 10 extended through bit 15).
The following table describes the behavior of the data result registers in the different
modes of operation.
Table 34-44. Data result register description
Conversion
mode
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Format
16-bit differential S D D D D D D D D D D D D D D D Signed 2's
complement
16-bit single-
ended
D D D D D D D D D D D D D D D D Unsigned right
justified
13-bit differential S S S S D D D D D D D D D D D D Sign extended
2's complement
12-bit single-
ended
0 0 0 0 D D D D D D D D D D D D Unsigned right
justified
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
812
Freescale Semiconductor, Inc.