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| K60P100M100SF2RM Datasheet, PDF (125/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual | |||
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Other peripherals
Peripheral
bridge 0
Register
access
Chapter 3 Chip Configuration
CMP
Module signals
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Figure 3-40. CMP configuration
Table 3-48. Reference links to related information
Related module
Comparator (CMP)
Port control
Reference
Comparator
System memory map
Clock distribution
Power management
Signal multiplexing
3.7.2.1 CMP input connections
The following table shows the fixed internal connections to the CMP.
CMP Inputs
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
CMP0
CMP0_IN0
CMP0_IN1
CMP0_IN2
CMP0_IN3
CMP0_IN4
VREF output/CMP0_IN5
Bandgap
6b DAC0 reference
CMP1
CMP1_IN0
CMP1_IN1
â
12b DAC0 reference/
CMP1_IN3
â
VREF output/CMP1_IN5
Bandgap
6b DAC1 reference
CMP2
CMP2_IN0
CMP2_IN1
â
CMP2_IN3
â
âCMP2_IN5
Bandgap
â
3.7.2.2 CMP external references
The 6-bit DAC sub-block supports selection of two references. For this device, the
references are connected as follows:
⢠VREF_OUT - Vin1 input
⢠VDD - Vin2 input
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
125
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