K60P100M100SF2RM Datasheet, PDF (1493/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
0
SBK
Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
UARTx_C2 field descriptions (continued)
Description
NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently not idle.
This can be determined by the S2[RAF] flag. If set to wake up an IDLE event and the channel is
already idle, it is possible that the UART will discard data since data must be received (or a LIN
break detect) after an IDLE is detected before IDLE is allowed to reasserted.
0 Normal operation.
1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware
wakes the receiver by automatically clearing RWU.
Send Break
Toggling SBK sends one break character (10, 11, or 12 logic 0s, if S2[BRK13] is cleared; 13 or 14 logic
0s, if S2[BRK13] is set). See Transmitting break characters for the number of logic 0s for the different
configurations. Toggling implies clearing the SBK bit before the break character has finished transmitting.
As long as SBK is set, the transmitter continues to send complete break characters (10, 11, or 12 bits, or
13 or 14 bits).This bit must be cleared when 7816E is set.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
51.3.5 UART Status Register 1 (UARTx_S1)
The S1 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. This register can also be polled by the MCU to check the status of these bits. To
clear a flag, the status register should be read followed by a read or write (depending on
interrupt flag type) to the UART Data Register. Other instructions can be executed
between the two steps as long as it does not compromise the handling of I/O, but the
order of operations is important for flag clearing. When a flag is configured to trigger a
DMA request, assertion of the associated DMA done signal from the DMA controller,
clears the flag.
NOTE
If the condition that results in the assertion of the flag, interrupt
or DMA request is not resolved prior to clearing the flag, the
flag (and interrupt/DMA request) will reassert. For example, if
the DMA or interrupt service routine failed to write sufficient
data to the transmit buffer to raise it above the watermark level,
the flag will reassert and generate another interrupt or DMA
request.
NOTE
Reading an empty data register to clear one of these flags
causes the FIFO pointers to get out of alignment. A receive
FIFO flush reinitializes the pointers.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1493