K60P100M100SF2RM Datasheet, PDF (157/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Source
UART 0
Block wait timer x
(ISO7816)
Guard time
x
violation (ISO7816)
UART 1
—
—
UART 2
—
—
Chapter 3 Chip Configuration
UART 3
—
UART 4
—
—
—
3.9.7 SDHC Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge
Register
access
Transfers
SDHC
Module signals
Topic
Full description
System memory map
Clocking
Power management
Transfers
Signal Multiplexing
Figure 3-63. SDHC configuration
Table 3-74. Reference links to related information
Related module
SDHC
Crossbar switch
Port control
Reference
SDHC
System memory map
Clock Distribution
Power management
Crossbar switch
Signal Multiplexing
3.9.7.1 SDHC clocking
In addition to the system clock, the SDHC needs a clock for the base for the external card
clock. There are four possible clock sources for this clock, selected by the SIM’s SOPT2
register:
• Core/system clock
• MCGPLLCLK or MCGFLLCLK
• EXTAL
• Bypass clock from off-chip (SDHC0_CLKIN)
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
157