K60P100M100SF2RM Datasheet, PDF (911/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 38 Programmable Delay Block (PDB)
38.3.1 Status and Control Register (PDBx_SC)
Addresses: PDB0_SC is 4003_6000h base + 0h offset = 4003_6000h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
0
LDMOD
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PRESCALER
W
TRGSEL
0
MULT
Reset 0
Field
31–20
Reserved
19–18
LDMOD
17
PDBEIE
16
SWTRIG
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDBx_SC field descriptions
Description
This read-only field is reserved and always has the value zero.
Load Mode Select
Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers, after 1 is written to
LDOK.
00 The internal registers are loaded with the values from their buffers immediately after 1 is written to
LDOK.
01 The internal registers are loaded with the values from their buffers when the PDB counter reaches
the MOD register value after 1 is written to LDOK.
10 The internal registers are loaded with the values from their buffers when a trigger input event is
detected after 1 is written to LDOK.
11 The internal registers are loaded with the values from their buffers when either the PDB counter
reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
PDB Sequence Error Interrupt Enable
This bit enables the PDB sequence error interrupt. When this bit is set, any of the PDB channel sequence
error flags generates a PDB sequence error interrupt.
0 PDB sequence error interrupt disabled.
1 PDB sequence error interrupt enabled.
Software Trigger
When PDB is enabled and the software trigger is selected as the trigger input source, writing 1 to this bit
reset and restarts the counter. Writing 0 to this bit has no effect. Reading this bit results 0.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
911