K60P100M100SF2RM Datasheet, PDF (1254/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definitions
USBx_ERRSTAT field descriptions
Field
7
BTSERR
6
Reserved
5
DMAERR
4
BTOERR
3
DFN8
2
CRC16
1
CRC5EOF
0
PIDERR
Description
This bit is set when a bit stuff error is detected. If set, the corresponding packet is rejected due to the
error.
This read-only field is reserved and always has the value zero.
This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given
the bus before it needs to receive or transmit data. If processing a TX transfer this would cause a transmit
data underflow condition. If processing a RX transfer this would cause a receive data overflow condition.
This interrupt is useful when developing device arbitration hardware for the microprocessor and the USB
Module to minimize bus request and bus grant latency. This bit is also set if a data packet to or from the
host is larger than the buffer size allocated in the BDT. In this case the data packet is truncated as it is put
into buffer memory.
This bit is set when a bus turnaround timeout error occurs. The USB Module contains a bus turnaround
timer that keeps track of the amount of time elapsed between the token and data phases of a SETUP or
OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted
from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data
fields be an integral number of bytes. If the data field was not an integral number of bytes, this bit is set.
This bit is set when a data packet is rejected due to a CRC16 error.
This error interrupt has two functions. When the USB Module is operating in peripheral mode
(HOSTMODEEN=0), this interrupt detects CRC5 errors in the token packets generated by the host. If set
the token packet was rejected due to a CRC5 error.
When the USB Module is operating in host mode (HOSTMODEEN=1), this interrupt detects End Of
Frame (EOF) error conditions. This occurs when the USB Module is transmitting or receiving data and the
SOF counter reaches zero. This interrupt is useful when developing USB packet scheduling software to
ensure that no USB transactions cross the start of the next frame.
This bit is set when the PID check field fails.
45.4.12 Error Interrupt Enable Register (USBx_ERREN)
The Error Interrupt Enable Register contains enable bits for each of the error interrupt
sources within the USB Module. Setting any of these bits enables the respective interrupt
source in the ERRSTAT register. Each bit is set as soon as the error conditions is
detected. Therefore, the interrupt does not typically correspond with the end of a token
being processed. This register contains the value of 0x00 after a reset.
Addresses: USB0_ERREN is 4007_2000h base + 8Ch offset = 4007_208Ch
Bit
7
6
5
4
3
Read
0
BTSERREN
DMAERREN BTOERREN DFN8EN
Write
Reset
0
0
0
0
0
2
1
0
CRC16EN CRC5EOFEN PIDERREN
0
0
0
1254
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.