K60P100M100SF2RM Datasheet, PDF (775/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

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Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
Table 32-15. CAU Commands (continued)
Command
Description
Name
8
AESIC
AES Inv Column Op
AESR
AES Shift Rows
AESIR
AES Inv Shift Rows
DESR
DES Round
DESK
DES Key Setup
HASH
SHS
Hash Function
Secure Hash Shift
MDS
Message Digest Shift
SHS2
Secure Hash Shift 2
ILL
Illegal Command
CMD
76543210
Operation
0x0D
CAx
InvMixColumns(CAx^Op1) →
CAx
0x0E0
ShiftRows(CA0-CA3) →
CA0-CA3
0x0F0
InvShiftRows(CA0-CA3)→
CA0-CA3
0x10
IP FP KS[1:0]
DES Round(CA0-CA3)
→CA0-CA3
0x11
0 0 C D DES Key Op(CA0-CA1)→
PC
CA0-CA1
Key Parity Error & CP →
CASR[1]
0x12
0 HF[2:0]
Hash Func(CA1-
CA3)+CAA→ CAA
0x130
CAA <<< 5→ CAA,
CAA→CA0, CA0→CA1,
CA1 <<< 30 → CA2,
CA2→CA3, CA3→CA4
0x140
CA3→CAA, CAA→CA1,
CA1→CA2, CA2→CA3,
0x150
CAA→CA0, CA0→CA1,
CA1 → CA2, CA2→CA3,
CA3 + CA8 →CA4,
CA4 → CA5, CA5 → CA6,
CA6 → CA7
0x1F0
0x1→CASR[IC]
32.6.3.1 Coprocessor No Operation (CNOP)
The CNOP command is the coprocessor no-op. It is issued by the MMCAU and
consumes a location in the MMCAU FIFO, but has no effect on any CAU register.
32.6.3.2 Load Register (LDR)
The LDR command loads CAx with the source data specified by the write data.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
775