K60P100M100SF2RM Datasheet, PDF (1706/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_RCCR field descriptions (continued)
Field
Description
used to control the amount of valid data in those 32 bits. In AC97 Mode of operation, if word length is set
to any value other than 16 bits, it will result in a word length of 20 bits.
12–8
DC
7–0
PM
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Number of Bits/Word: 2; Supported in Implementation: No.
Number of Bits/Word: 4; Supported in Implementation: No.
Number of Bits/Word: 6; Supported in Implementation: No.
Number of Bits/Word: 8; Supported in Implementation: Yes.
Number of Bits/Word: 10; Supported in Implementation: Yes.
Number of Bits/Word: 12; Supported in Implementation: Yes.
Number of Bits/Word: 14; Supported in Implementation: No.
Number of Bits/Word: 16; Supported in Implementation: Yes.
Number of Bits/Word: 18; Supported in Implementation: Yes.
Number of Bits/Word: 20; Supported in Implementation: Yes.
Number of Bits/Word: 22; Supported in Implementation: Yes.
Number of Bits/Word: 24; Supported in Implementation: Yes.
Number of Bits/Word: 26; Supported in Implementation: No.
Number of Bits/Word: 28; Supported in Implementation: No.
Number of Bits/Word: 30; Supported in Implementation: No.
Number of Bits/Word: 32; Supported in Implementation: No.
Frame Rate Divider Control.
These bits are used to control the divide ratio for the programmable frame rate dividers. The divide ratio
works on the word clock. In Normal mode, this ratio determines the word transfer rate. In Network mode,
this ratio sets the number of words per frame. The divide ratio ranges from 1 to 32 in Normal mode and
from 2 to 32 in Network mode. In Normal mode, a divide ratio of 1 (DC=00000) provides continuous
periodic data word transfer. A bit-length frame sync must be used in this case.
These bits can be programmed with values ranging from "00000" to "11111" to control the number of
words in a frame.
Prescaler Modulus Select.
These bits control the prescale divider in the clock generator. This prescaler is used only in Internal Clock
mode to divide the internal clock . The bit clock output is available at the clock port. A divide ratio from 1
to 256 (PM[7:0] = 0x00 to 0xFF) can be selected.
53.3.12 I²S FIFO Control/Status Register (I2Sx_FCSR)
The following table indicates the status of the Transmit FIFO Empty flag, with different
settings of the Transmit FIFO WaterMark bits and varying amounts of data in the Tx
FIFO.
Table 53-40. Status of Transmit FIFO Empty Flag
Transmit FIFO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Watermark
(TFWM)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Table continues on the next page...
1706
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.