K60P100M100SF2RM Datasheet, PDF (806/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Register Definition
ADC memory map (continued)
Absolute
address
(hex)
Register name
400B_B03C
ADC plus-side general calibration value register
(ADC1_CLP4)
400B_B040
ADC plus-side general calibration value register
(ADC1_CLP3)
400B_B044
ADC plus-side general calibration value register
(ADC1_CLP2)
400B_B048
ADC plus-side general calibration value register
(ADC1_CLP1)
400B_B04C
ADC plus-side general calibration value register
(ADC1_CLP0)
Width
(in bits)
Access
Reset value
32
R/W 0000_0200h
32
R/W 0000_0100h
32
R/W 0000_0080h
32
R/W 0000_0040h
32
R/W 0000_0020h
400B_B050 ADC PGA register (ADC1_PGA)
32
R/W 0000_0000h
400B_B054
ADC minus-side general calibration value register
(ADC1_CLMD)
400B_B058
ADC minus-side general calibration value register
(ADC1_CLMS)
400B_B05C
ADC minus-side general calibration value register
(ADC1_CLM4)
400B_B060
ADC minus-side general calibration value register
(ADC1_CLM3)
400B_B064
ADC minus-side general calibration value register
(ADC1_CLM2)
400B_B068
ADC minus-side general calibration value register
(ADC1_CLM1)
400B_B06C
ADC minus-side general calibration value register
(ADC1_CLM0)
32
R/W 0000_000Ah
32
R/W 0000_0020h
32
R/W 0000_0200h
32
R/W 0000_0100h
32
R/W 0000_0080h
32
R/W 0000_0040h
32
R/W 0000_0020h
Section/
page
34.3.13/
820
34.3.14/
821
34.3.15/
821
34.3.16/
822
34.3.17/
822
34.3.18/
823
34.3.19/
824
34.3.20/
825
34.3.21/
825
34.3.22/
826
34.3.23/
826
34.3.24/
827
34.3.25/
827
34.3.1 ADC status and control registers 1 (ADCx_SC1n)
The SC1A register is used for both software and hardware trigger modes of operation.
To allow sequential conversions of the ADC to be triggered by internal peripherals, the
ADC can have more then one status and control register: one for each conversion. The
SC1B-SC1n registers indicate potentially multiple SC1 registers for use only in hardware
trigger mode. Refer to the Chip Configuration information about the number of SC1n
registers specific to this device. The SC1n registers have identical fields, and are used in
a "ping-pong" approach to control ADC operation.
At any one point in time, only one of the SC1n registers is actively controlling ADC
conversions. Updating SC1A while SC1n is actively controlling a conversion is allowed
(and vice-versa for any of the SC1n registers specific to this MCU).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
806
Freescale Semiconductor, Inc.