K60P100M100SF2RM Datasheet, PDF (819/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Addresses: ADC0_MG is 4003_B000h base + 30h offset = 4003_B030h
ADC1_MG is 400B_B000h base + 30h offset = 400B_B030h
Chapter 34 Analog-to-Digital Converter (ADC)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
ADCx_MG field descriptions
Field
31–16
Reserved
15–0
MG
Description
This read-only field is reserved and always has the value zero.
Minus-side gain
34.3.11 ADC plus-side general calibration value register
(ADCx_CLPD)
The plus-side general calibration value registers (CLPx) contain calibration information
that is generated by the calibration function. These registers contain seven calibration
values of varying widths: CLP0[5:0], CLP1[6:0], CLP2[7:0], CLP3[8:0], CLP4[9:0],
CLPS[5:0], and CLPD[5:0]. CLPx are automatically set once the self calibration
sequence is done (CAL is cleared). If these registers are written by the user after
calibration, the linearity error specifications may not be met.
Addresses: ADC0_CLPD is 4003_B000h base + 34h offset = 4003_B034h
ADC1_CLPD is 400B_B000h base + 34h offset = 400B_B034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
CLPD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
ADCx_CLPD field descriptions
Field
31–6
Reserved
5–0
CLPD
Description
This read-only field is reserved and always has the value zero.
Calibration value
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
819