K60P100M100SF2RM Datasheet, PDF (1333/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
1
ERRINT
0
WAKINT
Chapter 48 CAN (FlexCAN)
CANx_ESR1 field descriptions (continued)
0 No such occurrence
1 FlexCAN module entered ‘Bus Off’ state
Error Interrupt
Description
This bit indicates that at least one of the Error Bits (bits 15-10) is set. If the corresponding mask bit
CTRL1[ERRMSK] is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. Writing
‘0’ has no effect.
0 No such occurrence
1 Indicates setting of any Error Bit in the Error and Status Register
Wake-Up Interrupt
This field applies when FlexCAN is in low power mode:
• Doze Mode
• Stop Mode
When a recessive-to-dominant transition is detected on the CAN bus and if the MCR[WAKMSK] bit is set,
an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’.
When MCR[SLFWAK] is negated, this flag is masked. The CPU must clear this flag before disabling the
bit. Otherwise it will be set when the SLFWAK is set again. Writing ‘0’ has no effect.
0 No such occurrence
1 Indicates a recessive to dominant transition was received on the CAN bus
48.3.10 Interrupt Masks 2 Register (CANx_IMASK2)
This register allows any number of a range of 32 Message Buffer Interrupts to be enabled
or disabled. It contains one interrupt mask bit per buffer, enabling the CPU to determine
which buffer generates an interrupt after a successful transmission or reception (i.e. when
the corresponding IFLAG2 bit is set).
Addresses: CAN0_IMASK2 is 4002_4000h base + 24h offset = 4002_4024h
CAN1_IMASK2 is 400A_4000h base + 24h offset = 400A_4024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUFHM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_IMASK2 field descriptions
Field
31–0
BUFHM
Description
Buffer MB_i Mask
Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt.
NOTE: Setting or clearing a bit in the IMASK2 Register can assert or negate an interrupt request, if the
corresponding IFLAG2 bit is set.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1333