K60P100M100SF2RM Datasheet, PDF (328/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Low-Voltage Detect (LVD) System
selectable trip voltage: high (V_LVDH) or low (V_LVDL). The trip voltage is selected by the
LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx
modes.
Two flags are available to indicate the status of the low-voltage detect system:
• The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF
bit is set when the internal supply voltage falls below the selected internal monitor
trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but
only if the internal supply has returned above the internal trip point; otherwise, the
LVDF bit remains set.
• The low voltage warning flag (LVWF) operates in a level sensitive manner. The
LVWF bit is set when the internal supply voltage falls below the selected internal
monitor trip point (VLVW). The LVWF bit is cleared by writing one to the
LVWACK bit, but only if the internal supply has returned above the internal trip
point; otherwise, the LVWF bit remains set.
14.3.1 LVD Reset Operation
By setting the LVDRE bit, the LVD generates a reset upon detection of a low voltage
condition. The low voltage detection threshold is determined by the LVDV bits. After an
LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises
above this threshold. The LVD bit in the SRS register is set following an LVD or power-
on reset.
14.3.2 LVD Interrupt Operation
By configuring the LVD circuit for interrupt operation (LVDIE set and LVDRE clear),
LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low
voltage condition. The LVDF bit is cleared by writing one to the LVDSC1[LVDACK]
bit.
14.3.3 Low-Voltage Warning (LVW) Interrupt Operation
The LVD system contains a low voltage warning flag (LVWF) to indicate that the supply
voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt,
which is enabled by setting the LVDSC2[LVWIE] bit. If enabled, an LVW interrupt
request occurs when the LVWF is set. LVWF is cleared by writing one to the
LVDSC2[LVWACK] bit.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
328
Freescale Semiconductor, Inc.