K60P100M100SF2RM Datasheet, PDF (1587/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
3
SDSTB
2
DLA
1
CDIHB
Chapter 52 Secured digital host controller (SDHC)
SDHC_PRSSTAT field descriptions (continued)
0b Bus clock is active
1b Bus clock is gated off
SD Clock Stable
Description
This status bit indicates that the internal card clock is stable. This bit is for the host driver to poll clock
status when changing the clock frequency. It is recommended to clear SYSCTL[SDCLKEN] bit to remove
glitch on the card clock when the frequency is changing.
0b Clock is changing frequency and not stable
1b Clock is stable
Data Line Active
This status bit indicates whether one of the DAT lines on the SD bus is in use.
In the case of read transactions:
This status indicates if a read transfer is executing on the SD bus. Changes in this value from 1 to 0,
between data blocks, generates a block gap event interrupt in the interrupt status register.
This bit will be set in either of the following cases:
• After the end bit of the read command.
• When writing a 1 to the PROCTL[CREQ] to restart a read transfer.
This bit will be cleared in either of the following cases:
1. When the end bit of the last data block is sent from the SD bus to the SDHC.
2. When the read wait state is stopped by a suspend command and the DAT2 line is released.
The SDHC will wait at the next block gap by driving read wait at the start of the interrupt cycle. If the read
wait signal is already driven (data buffer cannot receive data), the SDHC can wait for a current block gap
by continuing to drive the read wait signal. It is necessary to support read wait in order to use the
suspend / resume function. This bit will remain 1 during read wait.
In the case of write transactions:
This status indicates that a write transfer is executing on the SD bus. Changes in this value from 1 to 0
generate a transfer complete interrupt in the interrupt status register.
This bit will be set in either of the following cases:
• After the end bit of the write command.
• When writing to 1 to the PROCTL[CREQ] to continue a write transfer.
This bit will be cleared in either of the following cases:
• When the SD card releases write busy of the last data block, the SDHC will also detect if the output
is not busy. If the SD card does not drive the busy signal after the CRC status is received, the
SDHC shall assume the card drive “Not busy”.
• When the SD card releases write busy, prior to waiting for write transfer, and as a result of a stop at
block gap request.
In the case of command with busy pending:
This status indicates that a busy state follows the command and the data line is in use. This bit will be
cleared when the DAT0 line is released.
0b DAT line inactive
1b DAT line active
Command Inhibit (DAT)
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1587