K60P100M100SF2RM Datasheet, PDF (908/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
PDBCHnDLY0
=
Ch n pre-trigger 0
BB[0], TOS[0] EN[0]
PDBCHnDLYm
=
Ch n pre-trigger m
BB[m], TOS[m] EN[m]
Ack 0
Pre-trigger 0
Ack m
Pre-trigger m
Sequence Error
Detection
ERR[M - 1:0]
Ch n trigger
PDBMOD
PDBCNT
PDB Counter
MULT
PRESCALER
Trigger-In 0
Trigger-In 1
Trigger-In 14
SWTRIG
TRIGSEL
=
Control
Logic
CONT
DACINTx
DAC Interval
Counter x
=
DAC interval trigger x
TOEx
EXTx
DAC ext trigger input x
DAC interval trigger x
POyDLY1
=
POyDLY2
=
Pulse-Out y
Pulse
Generation
Pulse-Out y
PDBPOEN[y]
PDBIDLY
=
TOEx
Figure 38-1. PDB Block Diagram
PDB interrupt
In this diagram, only one PDB channel n, one DAC interval trigger x, and one Pulse-Out
y is shown. The PDB enable control logic and the sequence error interrupt logic is not
shown.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
908
Freescale Semiconductor, Inc.