K60P100M100SF2RM Datasheet, PDF (695/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Signal
FB_A[31:0]
FB_D[31:0]/
FB_AD[31:0]
FB_CS[5:0]
FB_BE_31_24
FB_BE_23_16
FB_BE_15_8
FB_BE_7_0
FB_OE
FB_R/W
FB_TS
FB_ALE
FB_TSIZ[1:0]
FB_TBST
FB_TA
FB_CLK
Chapter 29 External Bus Interface (FlexBus)
Table 29-1. FlexBus Signal Summary
Description
I/O
In a non-multiplexed configuration, this is the address bus.
O
In a non-multiplexed configuration, this is the data bus. In a multiplexed
I/O
configuration this bus is the address/data bus, FB_AD[31:0]. In non-
multiplexed and multiplexed configurations, during the first cycle, this bus
drives the upper address byte, addr[31:24].
General purpose chip-selects. The actual number of chip selects available
O
depends upon the device and its pin configuration.
Byte enables
O
Output enable
O
Read/write. 1 = Read, 0 = Write
O
Transfer start
O
Address latch enable (an inverse of FB_TS)
O
Transfer size
O
Burst transfer indicator
O
Transfer acknowledge
I
FlexBus clock output
O
29.2.1 Address and Data Buses (FB_An, FB_Dn, FB_ADn)
In non-multiplexed mode, the FB_A[31:0] and FB_D[31:0] buses carry the address and
data, respectively. The number of byte lanes carrying the data is determined by the port
size associated with the matching chip select.
In multiplexed mode, the FB_AD[31:0] bus carries the address and data. The full 32-bit
address is driven on the first clock of a bus cycle (address phase). Following the first
clock, the data is driven on the bus (data phase). During the data phase, the address
continues driving on the pins not used for data. For example, in 16-bit mode the lower
address continues driving on FB_AD[15:0] and in 8-bit mode the lower address continues
driving on FB_AD[23:0].
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
695