K60P100M100SF2RM Datasheet, PDF (767/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Code
7
8
9
10
Register
DES
General
—
purpose register
5 (CA5)
General
—
purpose register
6 (CA6)
General
—
purpose register
7 (CA7)
General
—
purpose register
8 (CA8)
Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
AES
—
MD5
—
SHA-1
W
SHA-256
F
—
—
—
G
—
—
—
H
—
—
—
W/T₁
The CAU only supports 32-bit operations and register accesses. All registers support
read, write, and ALU operations. However, only bits 1–0 of the CASR are writeable. Bits
31–2 of the CASR must be written as 0 for compatibility with future versions of the
CAU.
The codes listed in this section are used in the memory-mapped commands. For more
details on this, see MMCAU Programming Model.
NOTE
In the following table, the "address" or "offset" refers to the
command code value for the CAU registers.
Absolute
address
(hex)
CAU memory map
Register name
Width
(in bits)
Access
Reset value
E008_1000 Status Register (CAU_CASR)
32
R/W 2000_0000h
E008_1001 Accumulator (CAU_CAA)
32
R/W 0000_0000h
E008_1002 General Purpose Register (CAU_CA0)
32
R/W 0000_0000h
E008_1003 General Purpose Register (CAU_CA1)
32
R/W 0000_0000h
E008_1004 General Purpose Register (CAU_CA2)
32
R/W 0000_0000h
E008_1005 General Purpose Register (CAU_CA3)
32
R/W 0000_0000h
E008_1006 General Purpose Register (CAU_CA4)
32
Table continues on the next page...
R/W 0000_0000h
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
767