K60P100M100SF2RM Datasheet, PDF (801/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

ADHWTSA
ADHWTSn
ADHWT
C om pare true ₁
Interrupt
VREF_O^MU^CT^{U STOP}
PGA
DADP0
DADP2
DADP3
AD4
AD23
TempP
VREF_OUT
PGA
DADM0
DADM2
DADM3
TempM
V _REFH
V_ALTH
V _REFL
V_ALTL
Conversion
Trigger
Control
Chapter 34 Analog-to-Digital Converter (ADC)
SC1A
ADTRG
SC1n
Control Registers (SC2, CFG1, CFG2)
ADACKEN
Async
Clock Gen
A D C K Clock
Control Sequencer
Divide
ADACK
Bus Clock
2
ALTCLK
A D V IN P
A D V IN M
SAR Converter
PG, MG
CLPx
CLMx
PG, MG
CLPx
CLMx
Offset Subtractor
Averager
ADCOFS
AVGE, AVGS
OFS
Calibration
CAL
CALF
SC3
Formatting
D
transfer
MODE
Compare
Logic
C V1
CV2
CV1:CV2
ACFE
ACFGT, ACREN
Compare true ₁
Figure 34-1. ADC block diagram
CFG1,2
RA
Rn
SC2
34.2 ADC Signal Descriptions
The ADC module supports up to 4 pairs of differential inputs and up to 24 single-ended
inputs. Each differential pair requires two inputs, DADPx and DADMx. The ADC also
requires four supply/reference/ground connections.
Table 34-1. ADC Signal Descriptions
Signal
Description
I/O
DADP[3:0]
Differential analog channel inputs
I
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
801