K60P100M100SF2RM Datasheet, PDF (219/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 9 Debug
2. Set the control level to 2 via zero-bit scans
3. Execute the Store Format (STFMT) command (00011) to set the scan format register
to 1149.7 scan format
9.3 Debug Port Pin Descriptions
The debug port pins default after POR to their JTAG functionality with the exception of
JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG
and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO
functions.
Table 9-2. Debug port pins
Pin Name
JTAG Debug Port
JTAG_TMS/
SWD_DIO
Type
I/O
JTAG_TCLK/ I
SWD_CLK
JTAG_TDI I
JTAG_TDO/ O
TRACE_SW
O
JTAG_TRST I
_b
Description
JTAG Test
Mode
Selection
JTAG Test
Clock
JTAG Test
Data Input
JTAG Test
Data Output
JTAG Reset I
cJTAG Debug Port
Type
I/O
Description
cJTAG Data
I
cJTAG Clock
-
-
O
Trace output
over a single
pin
cJTAG Reset -
SWD Debug Port
Internal Pull-
up\Down
Type
Description
I/O
Serial Wire Pull-up
Data
I
Serial Wire Pull-down
Clock
-
-
Pull-up
O
Trace output N/C
over a single
pin
-
Pull-up
9.4 System TAP connection
The system JTAG controller is connected in parallel to the ARM TAP controller. The
system JTAG controller IR codes overlay the ARM JTAG controller IR codes without
conflict. Refer to the IR codes table for a list of the available IR codes. The output of the
TAPs (TDO) are muxed based on the IR code which is selected. This design is fully
JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset,
ARM's IDCODE (IR=4'b1110) is selected.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
219