K60P100M100SF2RM Datasheet, PDF (1083/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 41 Low power timer (LPTMR)
The LPTMR counter register cannot be initialized, but can be read at any time. Reading
the LPTMR counter register at the same time as it is incrementing may return invalid data
due to synchronization of the read data bus. If it is necessary for software to read the
LPTMR counter register, it is recommended that two read accesses are performed and
software verifies that the same data was returned for both reads.
41.4.6 LPTMR hardware trigger
The LPTMR hardware trigger asserts at the same time the timer compare flag is set and
can be used to trigger hardware events in other peripherals without software intervention.
The hardware trigger is always enabled.
When the LPTMR compare register is set to zero with the free running counter bit clear,
the LPTMR hardware trigger will assert on the first compare and does not negate. When
the LPTMR compare register is set to a non-zero value (or if the free running counter bit
is set) the LPTMR hardware trigger will assert on each compare and negate on the
following increment of the LPTMR counter register.
41.4.7 LPTMR interrupt
The LPTMR interrupt is generated whenever the CSR[TIE] and CSR[TCF] are set. The
CSR[TCF] is cleared by disabling the LPTMR or by writing a logic one to it.
The CSR[TIE] can be altered and the CSR[TCF] can be cleared while the LPTMR is
enabled.
The LPTMR interrupt is generated asynchronously to the system clock and can be used to
generate a wakeup from any low power mode, including the low leakage modes
(provided the LPTMR is enabled as a wakeup source).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1083