K60P100M100SF2RM Datasheet, PDF (1024/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
system clock
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
Figure 39-222. FTM Counter Synchronization with (SYNCMODE = 0), (REINIT = 1),
(PWMSYNC = 0), and (Software Trigger Was Used)
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
Figure 39-223. FTM Counter Synchronization with (SYNCMODE = 0), (HWTRIGMODE =
0), (REINIT = 1), (PWMSYNC = 0), and (a Hardware Trigger Was Used)
If (SYNCMODE = 0), (REINIT = 1) and (PWMSYNC = 1) then this synchronization is
made on the next enabled hardware trigger. The TRIGn bit is cleared according to
Hardware Trigger.
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
Figure 39-224. FTM Counter Synchronization with (SYNCMODE = 0), (HWTRIGMODE =
0), (REINIT = 1), (PWMSYNC = 1), and (a Hardware Trigger Was Used)
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.