K60P100M100SF2RM Datasheet, PDF (1631/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Valid
End
Int
Chapter 52 Secured digital host controller (SDHC)
Table 52-36. Format of the ADMA2 descriptor table (continued)
Valid = 1 indicates this line of descriptor is effective. If valid = 0 generate ADMA error interrupt and
stop ADMA.
End = 1 indicates current descriptor is the ending one.
Int = 1 generates DMA interrupt when this descriptor is done.
System Address Register points to
the head node of Descriptor Table
Advanced DMA
System Memory
Address
Descriptor Table
Length Attribute
System Address Register
Data Length (invisible)
Data Address (invisible)
DMA Interrupt
Address1 Length1
Address2 Length2
Tran
Link
Address
Address3
Attribute
Tran, End
Flags
State
Machine
SDMA
Transfer Complete
ADMA Error
Page Data
Page Data
Figure 52-33. Concept and access method of ADMA2 descriptor table
52.5.2.4.2 ADMA interrupt
If the 'interrupt' flag of descriptor is set, ADMA will generate an interrupt according to
different type descriptor:
For ADMA1:
• Set type descriptor: interrupt is generated when data length is set.
• Tran type descriptor: interrupt is generated when this transfer is complete.
• Link type descriptor: interrupt is generated when new descriptor address is set.
• Nop type descriptor: interrupt is generated just after this descriptor is fetched.
For ADMA2:
• Tran type descriptor: interrupt is generated when this transfer is complete.
• Link type descriptor: interrupt is generated when new descriptor address is set.
• Nop/Rsv type descriptor: interrupt is generated just after fetch this descriptor.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1631