K60P100M100SF2RM Datasheet, PDF (1629/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

• Valid/Invalid descriptor.
• Nop descriptor.
• Set data length descriptor.
• Set data address descriptor.
• Link descriptor.
• Interrupt flag and end flag in descriptor.
Chapter 52 Secured digital host controller (SDHC)
For ADMA2, including the following descriptors:
• Valid/Invalid descriptor.
• Nop descriptor.
• Rsv descriptor.
• Set data length & address descriptor.
• Link descriptor.
• Interrupt flag and end flag in descriptor.
ADMA2 deals with the lower 32-bit first, and then the higher 32-bit. If the 'Valid' flag of
descriptor is 0, it will ignore the high 32-bit. Address field shall be set on word
aligned(lower 2-bit is always set to 0). Data length is in byte unit.
ADMA will start read/write operation after it reaches the tran state, using the data length
and data address analyzed from most recent descriptor(s).
For ADMA1, the valid data length descriptor is the last set type descriptor before tran
type descriptor. Every tran type will trigger a transfer, and the transfer data length is
extracted from the most recent set type descriptor. If there is no set type descriptor after
the previous trans descriptor, the data length will be the value for previous transfer, or 0 if
no set descriptor is ever met.
For ADMA2, tran type descriptor contains both data length and transfer data address, so
only a tran type descriptor can start a data transfer
Table 52-35. Format of the ADMA1 descriptor table
Address/page field
31
12
Address or data length
Address/page field
11
6
000000
5
Act2
4
Act1
Attribute field
3
2
0
Int
1
0
End Valid
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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