K60P100M100SF2RM Datasheet, PDF (1256/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definitions
45.4.13 Status Register (USBx_STAT)
The Status Register reports the transaction status within the USB Module. When the
processor's interrupt controller has received a TOKDNE interrupt the Status Register
should be read to determine the status of the previous endpoint communication. The data
in the status register is valid when the TOKDNE interrupt bit is asserted. The STAT
register is actually a read window into a status FIFO maintained by the USB Module.
When the USB Module uses a BD, it updates the Status Register. If another USB
transaction is performed before the TOKDNE interrupt is serviced, the USB Module
stores the status of the next transaction in the STAT FIFO. Thus the STAT register is
actually a four byte FIFO that allows the processor core to process one transaction while
the SIE is processing the next transaction. Clearing the TOKDNE bit in the ISTAT
register causes the SIE to update the STAT register with the contents of the next STAT
value. If the data in the STAT holding register is valid, the SIE immediately reasserts to
TOKDNE interrupt.
Addresses: USB0_STAT is 4007_2000h base + 90h offset = 4007_2090h
Bit
7
Read
Write
Reset
0
6
5
ENDP
0
0
4
3
2
1
0
TX
ODD
0
0
0
0
0
0
USBx_STAT field descriptions
Field
7–4
ENDP
3
TX
2
ODD
1–0
Reserved
Description
This four-bit field encodes the endpoint address that received or transmitted the previous token. This
allows the processor core to determine which BDT entry was updated by the last USB transaction.
Transmit Indicator
0 The most recent transaction was a Receive operation.
1 The most recent transaction was a Transmit operation.
this bit is set if the last Buffer Descriptor updated was in the odd bank of the BDT.
This read-only field is reserved and always has the value zero.
1256
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.