K60P100M100SF2RM Datasheet, PDF (1621/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

• External DMA mode:
Chapter 52 Secured digital host controller (SDHC)
• For a read operation, when there are more words received in the buffer than the
amount set in the RDWML register, a DMA request is sent out to inform the
external DMA to fetch the data. The request will be immediately de-asserted
when there is an access on the DATPORT register. If the number of words in the
buffer after the current burst meets or exceeds RDWML value, then the DMA
request is asserted again. So for instance if there are twice as many words in the
buffer than the RDWML value, there are two successive DMA requests with
only one cycle of de-assertion between. The write operation is similar.
Note the accesses CPU polling mode and external DMA mode both use the IP
bus, and if the external DMA is enable, in both modes an external DMA request
is sent out whenever the buffer is ready.
• Internal DMA mode (includes simple and advanced DMA access's):
• The internal DMA access, either by simple or advanced DMA, is over the
crossbar switch bus. For internal DMA access mode, the external DMA request
will never be sent out.
For a read operation, when there are more words in the buffer than the amount set in the
WML register, the internal DMA starts fetching data over the crossbar switch bus. Except
INCR4 and INCR8, the burst type is always INCR mode and the burst length depends on
the shortest of following factors:
1. Burst length configured in the burst length field of the WML register
2. Watermark level boundary
3. Block size boundary
4. Data boundary configured in the current descriptor (if the ADMA is active)
5. 1 KB address boundary
Write operation is similar.
Sequential and contiguous access is necessary to ensure the pointer address value is
correct. Random or skipped access is not possible. The byte order, by reset, is little
endian mode. The actually byte order is swapped inside the buffer, according to the
endian mode configured by software, as illustrated in the following diagrams. For a host
write operation, byte order is swapped after data is fetched from the buffer and ready to
send to the SD bus. For a host read operation, byte order is swapped before the data is
stored into the buffer.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1621