K60P100M100SF2RM Datasheet, PDF (763/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 32
Memory-Mapped Cryptographic Acceleration Unit
(MMCAU)
32.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The Memory-Mapped Cryptographic Acceleration Unit (MMCAU) is a coprocessor that
is connected to the processor's Private Peripheral Bus (PPB). It supports the hardware
implementation of a set of specialized operations to improve the throughput of software-
based security encryption/decryption operations and message digest functions.
The MMCAU supports acceleration of the DES, 3DES, AES, MD5, SHA-1 and
SHA-256 algorithms. Freecsale provides an optimized, callable C-function library that
provides the appropriate software building blocks to implement higher-level security
functions.
32.2 MMCAU Block Diagram
The following simplified block diagram illustrates the MMCAU.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
763