K60P100M100SF2RM Datasheet, PDF (309/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

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Chapter 13 Mode Controller
Table 13-2. Power mode transition triggers (continued)
From
Run
To
VLPR
Trigger Conditions
Reduce system, bus and core frequency to 2 MHz or less,
Flash access limited to 1MHz.
AVLP=1,
Set RUNM = 10.
NOTE: Poll VLPRS bit before transitioning out of VLPR
mode.
VLPR
Run
Set RUNM = 00 or
Interrupt with LPWUI =1 or
Reset.
NOTE: Poll REGONS bit before increasing frequency.
VLPR
VLPW
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
clear, controlled in System Control Register in ARM core
VLPW
VLPW
VLPR
Run
Interrupt with LPWUI = 0
Interrupt with LPWUI = 1 or
Reset
VLPR
VLPS
LPLLSM=000 or 010, Sleep-now or sleep-on-exit modes
entered with SLEEPDEEP set, controlled in System Control
Register in ARM core
VLPS
Run
VLPR
VLPS
Interrupt with LPWUI = 0
AVLP=1, LPLLSM=010, Sleep-now or sleep-on-exit modes
entered with SLEEPDEEP set, controlled in System Control
Register in ARM core
NOTE: Hardware will set LPWUI and will remain set until
software clears.
VLPS
Run
Run
Interrupt with LPWUI =1 or
Reset
LLS
LPLLSM=011, Sleep-now or sleep-on-exit modes entered
with SLEEPDEEP set, controlled in System Control Register
in ARM core
LLS
Run
Wakeup from enabled LLWU input source or RESET pin
VLPR
LLS
LPLLSM=011, Sleep-now or sleep-on-exit modes entered
with SLEEPDEEP set, controlled in System Control Register
in ARM core
Run
VLLS(3,2,1) LPLLSM = (see PMCTRL register description for VLLS
configuration),
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, controlled in System Control Register in ARM core
VLLS(3,2,1)
Run
Wakeup from enabled LLWU input source or RESET pin
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
309