K60P100M100SF2RM Datasheet, PDF (241/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chip signal name
FB_CLKOUT
Chapter 10 Signal Multiplexing and Signal Descriptions
Table 10-10. FlexBus Signal Descriptions
Module signal Description
I/O
name
FB_CLK
FlexBus clock output
O
FB_AD[31:0] ¹
FB_D[31:0]/
In a non-multiplexed configuration, this is the data bus. In a
I/O
FB_AD[31:0]
multiplexed configuration this bus is the address/data bus,
FB_AD[31:0]. In non-multiplexed and multiplexed configurations,
during the first cycle, this bus drives the upper address byte,
addr[31:24].
FB_CS[5:0] ²
FB_CS[5:0]
General purpose chip-selects. The actual number of chip selects
O
available depends upon the device and its pin configuration.
FB_BE31_24_BLS7 FB_BE_31_24 Byte enables
O
_0,
FB_BE23_16_BLS1
FB_BE_23_16
5_8,
FB_BE_15_8
FB_BE15_8_BLS23
_16,
FB_BE_7_0
FB_BE7_0_BLS31_
24³
FB_OE
FB_OE
Output enable
O
FB_R W
FB_R/W
Read/write. 1 = Read, 0 = Write
O
FB_TS/ FB_ALE
FB_TS
Transfer start
O
FB_TSIZ[1:0]
FB_TSIZ[1:0]
Transfer size
O
FB_TA⁴
FB_TA
Transfer acknowledge
I
FB_TBST
FB_TBST
Burst transfer indicator
O
1. FB_AD[23:21] not available on 100-LQFP devices.
2. FB_CS3not available on 100-LQFP devices.
3. FB_BE7_0_BLS31_24not available on 100-LQFP devices.
4. FB_TAnotavailable on 100-LQFP devices.
10.4.5 Analog
Table 10-11. ADC 0 Signal Descriptions
Chip signal name
ADC0_DP3,
PGA0_DP,
ADC0_DP[1:0]
Module signal
name
DADP[3:0]
Description
Differential analog channel inputs
ADC0_DM3,
PGA0_DM,
ADC0_DM[1:0]
DADM[3:0]
Differential analog channel inputs
ADC0_SE[18,17,15:
12,9:418,17,15:12,9:
4]
AD[23:4]
Single-ended analog channel inputs
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
I/O
I
I
I
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