K60P100M100SF2RM Datasheet, PDF (1686/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_TX1 field descriptions (continued)
Field
Description
Example: If Tx FIFO0 is in use and you write Data1 - 16 to TX0, Data16 does not overwrite Data1. Data1 -
15 are stored in the FIFO while Data16 is discarded. Example: If Tx FIFO0 is not in use and you write
Data1, Data2 to TX0, then Data2 does not overwrite Data1 and is discarded.
NOTE: Enable I²S (CR[I2SEN]=1) before writing to the I²S transmit data registers.
53.3.3 I²S Receive Data Registers 0 (I2Sx_RX0)
The RX0 registers store the data received by the I2S.
Addresses: I2S0_RX0 is 4002_F000h base + 8h offset = 4002_F008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RX0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RX0 field descriptions
Field
31–0
RX0
I2S Receive Data
Description
These bits store the data received by the I²S. These are implemented as the first word of their respective
Rx FIFOs. These bits receive data from the RXSR depending on the mode of operation. In case both
FIFOs are in use, data is transferred to each data register alternately. RX1 can only be used in two-
channel mode of operation.
53.3.4 I²S Receive Data Registers 1 (I2Sx_RX1)
The RX1 registers store the data received by the I2S.
Addresses: I2S0_RX1 is 4002_F000h base + Ch offset = 4002_F00Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RX1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RX1 field descriptions
Field
31–0
RX1
I2S Receive Data
Description
These bits store the data received by the I²S. These are implemented as the first word of their respective
Rx FIFOs. These bits receive data from the RXSR depending on the mode of operation. In case both
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.