K60P100M100SF2RM Datasheet, PDF (1791/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 56 JTAG Controller (JTAGC)
56.3 Register description
This section provides a detailed description of the JTAGC block registers accessible
through the TAP interface, including data registers and the instruction register. Individual
bit-level descriptions and reset states of each register are included. These registers are not
memory-mapped and can only be accessed through the TAP.
56.3.1 Instruction register
The JTAGC block uses a 4-bit instruction register as shown in the following figure. The
instruction register allows instructions to be loaded into the block to select the test to be
performed or the test data register to be accessed or both. Instructions are shifted in
through TDI while the TAP controller is in the Shift-IR state, and latched on the falling
edge of TCK in the Update-IR state. The latched instruction value can only be changed in
the Update-IR and Test-Logic-Reset TAP controller states. Synchronous entry into the
Test-Logic-Reset state results in the IDCODE instruction being loaded on the falling
edge of TCK. Asynchronous entry into the Test-Logic-Reset state results in asynchronous
loading of the IDCODE instruction. During the Capture-IR TAP controller state, the
instruction shift register is loaded with the value 0001b , making this value the register's
read value when the TAP controller is sequenced into the Shift-IR state.
R
W
Reset:
3
2
1
0
0
0
0
1
Instruction Code
0
0
0
1
Figure 56-2. Instruction register
56.3.2 Bypass register
The bypass register is a single-bit shift register path selected for serial data transfer
between TDI and TDO when the BYPASS, CLAMP, HIGHZ or reserve instructions are
active. After entry into the Capture-DR state, the single-bit shift register is set to a logic
0. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1791